1. Field of the Invention
The present invention relates generally to electronic carrier boards, and more particularly to an electronic carrier board applicable to surface mounted technology (SMT).
2. Description of Related Art
With the rapid development of IC manufacturing technology, electronic elements have been continuously designed and fabricated to have a minimized profile. Meanwhile, based on large-scale and highly integrated electronic circuits, IC-based products possess more complete functionality.
Conventionally, electronic elements are mounted on an electronic circuit board such as a printed circuit board (PCB), a circuit board or a substrate by through hole technology (THT). However, as the electronic elements used in the THT cannot be further reduced in size, the electronic elements occupy large spaces of the electronic carrier board. In addition, the electronic carrier board needs to have through holes corresponding to the pins of the electronic elements. Also, solder joints formed between the electronic elements and the electronic carrier board are relatively large. Due to these drawbacks, surface mounted technology (SMT) is widely employed nowadays in the mounting process of electronic elements for efficiently mounting electronic elements to an electronic carrier board.
By the THT, through holes need to be formed in an electronic carrier board for accommodating the pins of the electronic elements and the back surface of the electronic carrier board cannot be efficiently used since solder joints are formed thereon. Accordingly, conventional through hole type elements have been replaced by surface mount type elements that can be much smaller in size.
In a conventional flip-chip ball grid array (FCBGA) package, an underfill is filled between a chip and surface of a substrate so as to encapsulate conductive bumps, thereby increasing the strength of the conductive bumps and supporting the chip. Meanwhile, a plurality of solder balls serving as I/O connections is mounted on the other surface of the substrate. Thus, the volume of the package is greatly reduced with the substrate size being close to the chip size. Meanwhile, the need of bond wires is eliminated, thereby reducing the resistance and improving the electrical performance. Related techniques are disclosed in U.S. Pat. No. 6,153,930, No. 6,400,036, No. 6,391,683, No. 5,892,289 and No. 5,218,234.
Referring to FIGS. 1A and 1B, a conventional electronic carrier board with a chip mounted thereon before being package is shown. Therein, a plurality of solder pads 11 spaced from each other is formed on predefined positions of the electronic carrier board 1, and a plurality of solder bumps 12 is mounted on the bottom surface of the chip 13. The solder bumps 12 are aligned with the solder pads 11, and the solder bumps 12 are reflowed to form ball shape so as to join the chip 13 and the electronic carrier board 1 together and establish electrical connection therebetween.
However, the chip 13 may be slightly displaced due to vibration transferred by a rail during a reflow process. Since the carrying surfaces of the solder pads 11 and the surface of the carrier board 1 are substantially parallel to each other, the displacement of the chip 13 can easily cause slide of the solder bumps 12 and further cause adjacent solder bumps 12 to join together, as shown in FIG. 1B. Thus, the solder bumps 12 and the solder pads 1I cannot be correctly positioned and a short circuit problem may occur. Even worse, it fails to establish electrical connection between the chip 13 and the electronic carrier board 1.
Also, referring to FIG. 2, as disclosed by U.S. Pat. No. 5,477,086, a round-shaped through hole 211 is formed in the center of a column-shaped solder pad 21 and an opening 212 is formed at one side of the through hole 211 such that a solder bump can be positioned on the solder pad 21 through the through hole 211 and the opening 212 permits gas to escape. However, the through hole 211 is required to be precisely located at the center of the solder pad 21 so as to prevent adjacent bumps from joining together. Otherwise, the desired effect cannot be achieved. Also, the precise alignment of the through hole 211 complicates the fabrication process and increases the fabrication cost and time.
Therefore, how to provide an electronic carrier board so as to overcome the above-described drawbacks has become urgent.